The present invention relates to a semiconductor integrated circuit device including a flip-flop circuit and, more particularly, to a semiconductor integrated circuit device which has its logical operation timing controlled by the clock synchronization of a flip-flop circuit arranged in a data transmission path. More specifically, the present invention relates to a technology which is effective if applied to a logical LSI such as a microprocessor or a microcomputer.
A logical LSI such as the microprocessor is enabled to perform a data processing, while preventing a malfunction easily, by arranging registers in the data transmission paths between the logical circuits including an arithmetic and logic operator, a multiplexer, a shifter, a decoder and a selector contained in the execution unit of the LSI and by synchronizing the individual registers in response to clock signals. The registers to be adopted are generally exemplified by a plurality of static flip-flop circuits which can latch data stably irrespective of the influences of coupling noises, a low leakage current and alpha rays.
This logical LSI has its performance determined by the clock signal cycle for regulating the operations of the static flip-flop circuits which are arranged in the data transmission paths. Specifically, if data are outputted from the registers, i.e., the static flip-flop circuits in synchronism with changes in the clock signals, they are subjected to a variety of logical operations. Thus, the cycle of the clock signals is determined so that a register at a subsequent stage may input the data in synchronism with the changes in the clock signals while being timed with the arrival of the operated result at the subsequent register.
Incidentally, such microprocessor is disclosed on pp. 124 to 138 of "NIKKEI ELECTRONICS (of Jul. 13, 1987)" issued by NIKKEI McGRAW-HILL.